An IFM Receiver on a Single PCB
Calculator-size instantaneous frequency measurement (IFM) units, including digital frequency and phase/frequency discriminators
Instantaneous frequency measurement (IFM) devices traditionally have been large, cumbersome assemblies comprising multiple PCBs with the RF sections, and analog and digital circuitry located on separate boards. This configuration is both complicated and costly, and results in large and expensive receiver systems. The new Micro series digital frequency discriminators (DFD) are calculator-sized units that are essentially IFM units on a single PCB. In addition, the new Micro series phase/frequency discriminators (PFD) add a phase measurement capability. These revolutionary new products implement the latest digital, analog and RF technology solution (DARTS) packaging to offer a major reduction in size, weight and power consumption over conventionally built units. The DARTS packaging functionally integrates the RF and digital portions of the product onto a single, multilayer laminated PCB assembly. The result is a compact, lightweight, low cost subassembly that provides 8 bits of frequency and 8 bits of phase discrimination on a pulse-by-pulse basis over a 512 MHz operating bandwidth from UHF to 6 GHz. In addition, programmable read-only memory (PROM) components enable frequency and phase calibration and correction, eliminating the need for costly phase matching of interconnect cables.
The DFD
The model 18 5000 DFD is an 8-bit IFM with 2 MHz of resolution covering a 150 to 550 MHz input frequency range. Figure 1 shows the DFD's basic block diagram. The unit comprises a multilayer laminated assembly combining the RF, digital and analog circuitry, as shown in Figure 2 . The RF portion is a multilayer stripline assembly containing surface-mount, blind-mate coaxial connectors, an RF power divider, a reference line, a 2 ns delay line, embedded layer-to-layer interconnects, phase discriminators and detector diodes.
The model 18 5000 DFD is an 8-bit IFM with 2 MHz of resolution covering a 150 to 550 MHz input frequency range. Figure 1 shows the DFD's basic block diagram. The unit comprises a multilayer laminated assembly combining the RF, digital and analog circuitry, as shown in Figure 2 . The RF portion is a multilayer stripline assembly containing surface-mount, blind-mate coaxial connectors, an RF power divider, a reference line, a 2 ns delay line, embedded layer-to-layer interconnects, phase discriminators and detector diodes.
The RF input is received through the RF input connector, distributed through the stripline layers and converted to baseband through recessed detector diodes installed directly on the stripline layer. This configuration allows the RF to be totally enclosed within the plated RF assembly and eliminates the need for additional shielding or isolation.
The analog/digital (A/D) section comprises eight PCB layers and is bonded directly to the RF section. The detected in-phase/quadrature (I/Q) differential video signals are fed to the A/D section through plated-through holes, and are passed through video amplification, filtering and, finally, to patented 8-bit ring digitizers. The ring digitizer is an application-specific IC developed to convert I/Q information directly to a digital phase word by comparing the relative amplitudes of the I/Q signals. Because this digitizer measures the I/Q ratio, it is insensitive to absolute voltage levels and, thus, provides good linearity in the presence of a varying RF input. The result is a single-chip solution for converting I/Q information to an 8-bit digital phase word without the need for a voltage reference circuit or video scaling and offset circuits. The 8-bit uncorrected phase word is brought to the output connector within 50 ns of the A/D strobe, and also is fed to the flash PROM on the card. This step permits calibration and correction, and is in-system programmable to allow for correction of errors at the system level.
The entire assembly measures 3.00" x 4.00" x 0.75" and dissipates less than 1 W. The addition of a limiting amplifier increases the dynamic range to –60 to +5 dBm and increases the power consumption to 2 W.
The DARTS process allows the devices to be fabricated as panels and uses low cost microwave materials for volume production. This technique coupled with the custom ring digitizer and the use of industrial-grade standard components provide an order-of-magnitude reduction in cost over conventional IFM products.
By scaling the RF components, the RF section can be modified to operate anywhere in the 2 to 6 GHz frequency band. The model 18 5100 DFD operates unambiguously over any 512 MHz band in the 2 to 6 GHz frequency range. Since the output first is corrected through a flash PROM, it can be programmed to start at cell zero at any user-specified frequency. This modification is performed at the point of manufacture prior to shipment or changed in the system by the user through the data connector. Frequencies up to 18 GHz are possible.
By adding another channel with an 8 ns RF delay line, a 10-bit frequency word with 0.5 MHz resolution is generated as in the models 18 
A5000 and 18 A5100, shown in Figure 3 . This configuration provides increased frequency measurement accuracy to 1 MHz RMS and increased frequency resolution.
A5000 and 18 A5100, shown in Figure 3 . This configuration provides increased frequency measurement accuracy to 1 MHz RMS and increased frequency resolution.
The PFD
Since the heart of the IFM is the phase discriminator, which, essentially, is a quadrature IF mixer (QIFM), the logical offshoot of the single-channel Micro DFD is a single-channel phase discriminator or QIFM. When used as a phase discriminator, the input cables must be phase matched to eliminate a phase slope with frequency. If the input frequency is known, the phase slope can be calibrated out.
Since the heart of the IFM is the phase discriminator, which, essentially, is a quadrature IF mixer (QIFM), the logical offshoot of the single-channel Micro DFD is a single-channel phase discriminator or QIFM. When used as a phase discriminator, the input cables must be phase matched to eliminate a phase slope with frequency. If the input frequency is known, the phase slope can be calibrated out.
A slight modification of the RF section of the two-channel, 10-bit IFM produces a PFD that provides both phase and frequency information. 
The reference-side RF input is split internally into two paths; one directed to a single-channel IFM that provides 8 bits of frequency determination (2 MHz resolution), and the other directed to the reference side of the phase discriminator, as shown inFigure 4 . The phase discriminator measures the phase difference between its inputs, producing output-detected video voltages that vary in amplitude as a function of the sine and cosine of the input phase difference. These voltages are fed to a ring digitizer that provides an 8-bit digital phase word in a single chip. By combining the frequency and phase words in a correction PROM, the phase can be calibrated in the system as a function of frequency. This process eliminates the need for phase matching the RF input cables, and compensates for any offset or slope that occurs across phase or frequency. Table 1 lists the DFD and PFD models and their key specifications.
The reference-side RF input is split internally into two paths; one directed to a single-channel IFM that provides 8 bits of frequency determination (2 MHz resolution), and the other directed to the reference side of the phase discriminator, as shown inFigure 4 . The phase discriminator measures the phase difference between its inputs, producing output-detected video voltages that vary in amplitude as a function of the sine and cosine of the input phase difference. These voltages are fed to a ring digitizer that provides an 8-bit digital phase word in a single chip. By combining the frequency and phase words in a correction PROM, the phase can be calibrated in the system as a function of frequency. This process eliminates the need for phase matching the RF input cables, and compensates for any offset or slope that occurs across phase or frequency. Table 1 lists the DFD and PFD models and their key specifications.
Table I
Key Specification | ||||||
Model
|
18 5010
|
18 5020
|
18 5000
|
18 5100
|
18 A5000
|
18 A5100
|
Type
|
PFD
|
PFD
|
DFD
|
DFD
|
DFD
|
DFD
|
Operating Frequency (GHz)
|
0.15 to 0.55
|
2.00 to 6.00
|
0.15 to 0.55
|
2.00 to 6.00
|
0.15 to 0.55
|
2.00 to 6.00
|
Pulse Width (min) (ns)
|
50
|
50
|
50
|
50
|
50
|
50
|
Dynamic Range* (dBm)
| ||||||
(min)
|
8
|
8
|
5
|
5
|
8
|
8
|
(max)
|
12
|
12
|
9
|
9
|
12
|
12
|
Signal Noise (dB min)
|
10
|
10
|
10
|
10
|
10
|
10
|
Frequency Measurement
| ||||||
Un
ambiguous (MHz) |
512
|
512
|
512
|
512
|
512
|
512
|
Data valid bit
|
yes
|
yes
|
yes
|
yes
|
yes
|
yes
|
Number of bits
|
8
|
8
|
8
|
8
|
10
|
10
|
Resolution (MHz)
|
2.0
|
2.0
|
2.0
|
2.0
|
0.5
|
0.5
|
Accuracy (MHz) RMS
|
4
|
4
|
4
|
4
|
1
|
1
|
Phase Measurement
| ||||||
Un ambiguous phase (º)
|
0 to 360
|
0 to 360
|
No Phase Measurement
| |||
Number of bits
|
8
|
8
| ||||
Resolution (º)
|
1.4
|
1.4
| ||||
Accuracy (º) RMS
|
2.8
|
2.8
| ||||
External Read
|
Yes
|
Yes
|
Yes
|
Yes
|
Yes
|
Yes
|
Temp (ºC)
|
-20 to 70
|
-20 to 70
|
-20 to 70
|
-20 to 70
|
-20 to 70
|
-20 to 70
|
Dimensions(")
|
6.00x4.00x 0.75
|
6.00x4.00x 0.75
|
3.00x4.00x 0.75
|
3.00x4.00x 0.75
|
6.00x4.00x 0.75
|
6.00x4.00x 0.75
|
Weight (lb)
|
0.5
|
0.5
|
0.3
|
0.3
|
0.5
|
0.5
|
Power Cons. (W)
|
2
|
2
|
1
|
1
|
2
|
2
|
*Increased dynamic range of -60 to +5 dBm is available on all DFD types
| ||||||
Additional Applications 
Since the phase discriminator essentially is a QIFM, the PFD can be used as a digital phase receiver, as shown in Figure 5 . In this case, the digital frequency output is used to tune an LO to within 10 MHz of the input frequency, which generates an IF at the difference frequency. This signal then can be sampled at a 20 MHz clock rate, which provides phase samples every 50 ns. If this bit stream is monitored over long pulses or over several pulses, the phase data stream can be processed to measure the difference frequency to a very fine resolution (approximately 1/(256 x observation time)). For example, for a 1 ms pulse, the frequency can be measured to a 4 kHz resolution, and 1 Hz resolution can be obtained for a 4 ms observation time.
Since the phase discriminator essentially is a QIFM, the PFD can be used as a digital phase receiver, as shown in Figure 5 . In this case, the digital frequency output is used to tune an LO to within 10 MHz of the input frequency, which generates an IF at the difference frequency. This signal then can be sampled at a 20 MHz clock rate, which provides phase samples every 50 ns. If this bit stream is monitored over long pulses or over several pulses, the phase data stream can be processed to measure the difference frequency to a very fine resolution (approximately 1/(256 x observation time)). For example, for a 1 ms pulse, the frequency can be measured to a 4 kHz resolution, and 1 Hz resolution can be obtained for a 4 ms observation time.
If a log amplifier is added in front of the PFD's reference input, amplitude information can be added to the phase information to generate an R, q representation of the input signal. By analyzing the phase and amplitude data together, a complex representation of the input signal can be generated that allows a wide range of parameters to be extracted, which is useful for signal analysis and characterization. A variation of this technique digitizes the I/Q signals independently, providing a complex measurement by outputting an I/Q or real and imaginary data stream.
ConclusionThe low cost and small size of these new DFDs and PFDs introduce several new areas of applications. Channelized receivers are more attractive because the Micro DFD provides a low cost IFM device that can be applied to each channel. The unit also can be used to measure frequency for setting the frequency of a digitally controlled LO or to fine tune a digitally controlled frequency source. What was once a complex and costly system block now is an easy-to-utilize component that can be incorporated by the system and subsystem designer.
